Increased circuit density is a critical goal of integrated circuit design and fabrication. In order to achieve higher density, a downscaling of the transistors included within the circuit is effectuated. Such downscaling is typically achieved by shrinking the overall dimensions (and operating voltages) of the transistors. This shrinking cannot, however, be achieved at the expense of electrical performance. This is where the challenge arises: how to reduce transistor dimensions while maintaining the electrical properties of the device.
Conventional planar FET devices formed on bulk semiconductor substrates are quickly reaching their downscaling limit. Integrated circuit designers are accordingly turning towards new process technologies, new supporting substrates and new transistor configurations to support smaller and smaller transistor sizes without sacrificing transistor performance. One such new supporting substrate technology concerns the use of silicon on insulator (SOI) substrates to support the fabrication of transistor devices of smaller size. An SOI substrate is formed of a top semiconductor (for example, silicon) layer over an insulating (for example, silicon dioxide) layer over a bottom semiconductor (for example, silicon) substrate layer. Further substrate development has reduced the thickness of the intervening insulating layer to about 50 nm to produce a substrate for use in transistor fabrication that is referred to as an extremely thin silicon on insulator (ETSOI) substrate. Still further substrate development has reduced the thicknesses of all substrate layers to produce a substrate for use in transistor fabrication that is referred to an ultra-thin body and buried oxide (UTBB) substrate where the thickness of the intervening insulating layer is about 25 nm (or less) and the thickness of the top semiconductor layer is about 5 nm to 10 nm.
In a transistor fabricated using a UTBB substrate, the channel region of the transistor is formed in the ultra-thin top semiconductor layer which is fully depleted and is beneficial for controlling short channel effects. The thinner intervening insulating layer supports an aggressive transistor scaling capability, and permits tuning of the transistor threshold voltage (Vt) through the application of a back bias to the bottom semiconductor substrate layer.
To isolate adjacent transistors from each other, it is known in the art to use shallow trench isolation (STI) techniques. With transistors formed on a UTBB substrate, the STI structure is preferably a high aspect ratio structure (for example, having a ratio of about 1:10) which extends through both the ultra-thin top semiconductor layer and the thinner intervening insulating layer to reach into the bottom semiconductor substrate layer. In a preferred implementation, the bottom of the STI structure is about 150 nm below the intervening insulating layer.
When forming an STI structure, a trench is formed adjacent the transistor active region extending through the ultra-thin top semiconductor layer and the thinner intervening insulating layer and into the bottom semiconductor substrate layer. The trench is then filled with an insulating material such as silicon dioxide to a level above the top surface of the ultra-thin top semiconductor layer. The deposited silicon dioxide is then recessed by an etching process (typically using hydrofluoric acid (HF)). The recessing process, however, creates a problem at the edge of the STI structure due to the formation of a divot having a depth that could extend through both the ultra-thin top semiconductor layer and the thinner intervening insulating layer of the UTBB substrate. If a conductive or semiconductive material used in subsequent transistor fabrication process steps fills this divot, an undesirable short circuit is created between the transistor source/drain region and the bottom semiconductor substrate layer.
The prior art recognizes this divot and short problem and teaches a solution whereby the trench formed adjacent the transistor active region is first lined with a protective liner material before the trench is filled with the insulating material. The protective liner material is specifically chosen to be resistant to the HF etch solution used to recess the deposited silicon dioxide which fills the trench. For example, the prior art teaches the use of high temperature iRAD silicon nitride (SiN) material for the protective trench liner.
This protective liner solution has not completely addressed the problem of divot and short formation. The reason for this is that silicon nitride (SiN) films are commonly used in integrated circuit fabrication processing. These SiN films are often patterned and etched and must at some point in the fabrication process be selectively removed. For example, a hot phosphoric acid treatment is often used to effectuate selective removal of the SiN material. Because the protective liner is also made of SiN, the recessing of a SiN layer in a subsequent transistor fabrication process step will also attack the SiN liner to form a divot at the edge of the STI structure. Depending on the etch budget, the divot may have a depth extending through both the ultra-thin top semiconductor layer and the thinner intervening insulating layer of the UTBB substrate. Subsequently deposited conductive or semiconductive material filling this divot can create a short circuit between the transistor source/drain region and the bottom semiconductor substrate layer.
In an alternate solution, the prior art teaches the use of a high k dielectric material for the trench liner. For example, HfO2 or HfSiOx materials are proposed for used as a trench liner. There is a concern, however, with introducing either of these materials into the semiconductor fabrication environment for fear of contamination. Thus, rather than introduce a new material to the process, those skilled in the art would prefer the use of more commonly used semiconductor fabrication materials which are also used in the formation of other semiconductor integrated circuit structures.
There is accordingly a need in the art to address the divot problem which may lead to short circuit defects at shallow trench isolation (STI) structures formed in a UTBB substrate. More specifically, a need exists to improve the process margin for STI fabrication to resist both the hydrofluoric acid etch used to recess silicon dioxide structures and the hot phosphoric acid etch used to recess silicon nitride structures.